Invention Grant
- Patent Title: Semiconductor device having electrical fuses with less power consumption and interconnection arrangement
- Patent Title (中): 具有电功率消耗较小的电熔丝和互连配置的半导体器件
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Application No.: US12723218Application Date: 2010-03-12
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Publication No.: US08331185B2Publication Date: 2012-12-11
- Inventor: Shigeki Obayashi , Toshiaki Yonezu , Takeshi Iwamoto , Kazushi Kono , Masashi Arakawa , Takahiro Uchida
- Applicant: Shigeki Obayashi , Toshiaki Yonezu , Takeshi Iwamoto , Kazushi Kono , Masashi Arakawa , Takahiro Uchida
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: McDermott Will & Emery LLP
- Priority: JP2006-145759 20060525
- Main IPC: G11C17/18
- IPC: G11C17/18

Abstract:
In fuse program circuits, fuse element FS is implemented using metal interconnect at third or higher layer of multilayer metal interconnect. In each fuse program circuit, program information and fuse select information are sequentially transferred using a scan flip-flops, and fuses are selectively and electrically blown one by one. The fuse program circuit provided with fuse elements that can be programmed even after packaging is implemented with low power consumption and a low occupation area.
Public/Granted literature
- US20100165775A1 SEMICONDUCTOR DEVICE HAVING ELECTRICAL FUSES WITH LESS POWER CONSUMPTION AND INTERCONNECTION ARRANGEMENT Public/Granted day:2010-07-01
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