Invention Grant
US08340112B2 Implementing enhanced link bandwidth in a headless interconnect chip
失效
在无头互连芯片中实现增强的链路带宽
- Patent Title: Implementing enhanced link bandwidth in a headless interconnect chip
- Patent Title (中): 在无头互连芯片中实现增强的链路带宽
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Application No.: US12731715Application Date: 2010-03-25
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Publication No.: US08340112B2Publication Date: 2012-12-25
- Inventor: Phillip Rogers Hillier, III , David Alan Shedivy , Kenneth Michael Valk
- Applicant: Phillip Rogers Hillier, III , David Alan Shedivy , Kenneth Michael Valk
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Joan Pennington
- Main IPC: H04L12/54
- IPC: H04L12/54

Abstract:
A method and circuit for implementing enhanced link bandwidth for a headless interconnect chip in a local rack interconnect system, and a design structure on which the subject circuit resides are provided. The headless interconnect chip includes a cut through switch and a store and forward switch. A packet is received from an incoming link to be transmitted on an outgoing link on the headless interconnect chip. Both the cut through switch and the store and forward switch are selectively used for moving packets received from the incoming link to the outgoing link on the headless interconnect chip.
Public/Granted literature
- US20110235652A1 IMPLEMENTING ENHANCED LINK BANDWIDTH IN A HEADLESS INTERCONNECT CHIP Public/Granted day:2011-09-29
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