Invention Grant
- Patent Title: Method for manufacturing laminated electronic component
- Patent Title (中): 叠层电子元件的制造方法
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Application No.: US12796688Application Date: 2010-06-09
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Publication No.: US08341815B2Publication Date: 2013-01-01
- Inventor: Tatsuo Kunishi , Yoshihiko Takano , Shigeyuki Kuroda , Akihiro Motoki , Hideyuki Kashio , Takashi Noji
- Applicant: Tatsuo Kunishi , Yoshihiko Takano , Shigeyuki Kuroda , Akihiro Motoki , Hideyuki Kashio , Takashi Noji
- Applicant Address: JP Kyoto
- Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee Address: JP Kyoto
- Agency: Keating & Bennet, LLP
- Priority: JP2005-314722 20051028
- Main IPC: H01G4/228
- IPC: H01G4/228

Abstract:
A laminate is prepared in which adjacent internal electrodes are electrically insulated from each other at an end surface at which the internal electrodes are exposed, a space between the adjacent internal electrodes, which is measured in the thickness direction of insulating layers, is about 10 μm or less when a withdrawn distance of the adjacent internal electrodes from the end surface is about 1 μm or less, and is about 20 μm or less when a protruding length of the adjacent internal electrodes from the end surface is at least about 0.1 μm. In an electroplating step, electroplating deposits deposited on the ends of the adjacent internal electrodes are grown so as to be connected to each other.
Public/Granted literature
- US20100243133A1 LAMINATED ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2010-09-30
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