Invention Grant
US08341835B1 Buildup dielectric layer having metallization pattern semiconductor package fabrication method
有权
具有金属化图形半导体封装制造方法的积层电介质层
- Patent Title: Buildup dielectric layer having metallization pattern semiconductor package fabrication method
- Patent Title (中): 具有金属化图形半导体封装制造方法的积层电介质层
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Application No.: US12387691Application Date: 2009-05-05
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Publication No.: US08341835B1Publication Date: 2013-01-01
- Inventor: Ronald Patrick Huemoeller , Sukianto Rusli , David Jon Hiner
- Applicant: Ronald Patrick Huemoeller , Sukianto Rusli , David Jon Hiner
- Applicant Address: US AZ Chandler
- Assignee: Amkor Technology, Inc.
- Current Assignee: Amkor Technology, Inc.
- Current Assignee Address: US AZ Chandler
- Agency: McKay and Hodgson, LLP
- Agent Serge J. Hodgson
- Main IPC: H05K3/30
- IPC: H05K3/30

Abstract:
A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.
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