Method for forming a transistor comprising high-k metal gate electrode structures including a polycrystalline semiconductor material and embedded strain-inducing semiconductor alloys

Invention Grant

US08343826B2 Method for forming a transistor comprising high-k metal gate electrode structures including a polycrystalline semiconductor material and embedded strain-inducing semiconductor alloys 有权

Title translation: 一种用于形成包括包括多晶半导体材料和嵌入式应变诱导半导体合金的高k金属栅电极结构的晶体管的方法

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Patent Title: Method for forming a transistor comprising high-k metal gate electrode structures including a polycrystalline semiconductor material and embedded strain-inducing semiconductor alloys
Patent Title (中): 一种用于形成包括包括多晶半导体材料和嵌入式应变诱导半导体合金的高k金属栅电极结构的晶体管的方法
Application No.: US13198209

Application Date: 2011-08-04
Publication No.: US08343826B2

Publication Date: 2013-01-01
Inventor: Stephan-Detlef Kronholz , Peter Javorka , Maciej Wiatr
Applicant: Stephan-Detlef Kronholz , Peter Javorka , Maciej Wiatr
Applicant Address: KY Grand Cayman
Assignee: GLOBALFOUNDRIES Inc.
Current Assignee: GLOBALFOUNDRIES Inc.
Current Assignee Address: KY Grand Cayman
Agency: Williams, Morgan & Amerson, P.C.
Priority: DE102010064291 20101228
Main IPC: H01L21/8238
IPC: H01L21/8238

Method for forming a transistor comprising high-k metal gate electrode structures including a polycrystalline semiconductor material and embedded strain-inducing semiconductor alloys

Abstract:

When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage on the basis of a silicon/germanium semiconductor alloy for adjusting appropriate electronic conditions in the channel region, the efficiency of a strain-inducing embedded semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by initiating a crystal growth in the silicon material of the gate electrode structure after the gate patterning process. In this manner, the negative strain of the threshold voltage adjusting silicon/germanium alloy may be reduced or compensated for.

Abstract(Chinese):

当在硅/锗半导体合金的基础上在早期制造阶段形成复杂的高k金属栅极电极结构以调整沟道区域中适当的电子条件时，应变诱导嵌入式半导体合金如硅 /锗合金，可以通过在栅极图案化工艺之后在栅电极结构的硅材料中引发晶体生长来增强。以这种方式，可以减小或补偿阈值电压调节硅/锗合金的负应变。

Public/Granted literature

US20120161250A1 Transistor Comprising High-K Metal Gate Electrode Structures Including a Polycrystalline Semiconductor Material and Embedded Strain-Inducing Semiconductor Alloys Public/Granted day:2012-06-28

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS