Invention Grant
- Patent Title: Recessed gate channel with low Vt corner
- Patent Title (中): 嵌入门通道低Vt角
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Application No.: US13363944Application Date: 2012-02-01
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Publication No.: US08343836B2Publication Date: 2013-01-01
- Inventor: Brent A. Anderson , Andres Bryant , Edward J. Nowak
- Applicant: Brent A. Anderson , Andres Bryant , Edward J. Nowak
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Richard M. Kotulak, Esq.
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region.
Public/Granted literature
- US20120190156A1 RECESSED GATE CHANNEL WITH LOW Vt CORNER Public/Granted day:2012-07-26
Information query
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