Invention Grant
US08343838B2 Method of reducing dislocation-induced leakage in a strained-layer field-effect transistor by implanting blocking impurity into the strained-layer
有权
通过将阻塞杂质注入到应变层中来减少应变层场效应晶体管中位错诱发的泄漏的方法
- Patent Title: Method of reducing dislocation-induced leakage in a strained-layer field-effect transistor by implanting blocking impurity into the strained-layer
- Patent Title (中): 通过将阻塞杂质注入到应变层中来减少应变层场效应晶体管中位错诱发的泄漏的方法
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Application No.: US12539235Application Date: 2009-08-11
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Publication No.: US08343838B2Publication Date: 2013-01-01
- Inventor: Steven J. Koester
- Applicant: Steven J. Koester
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Louis J. Percello, Esq.
- Main IPC: H01L21/8258
- IPC: H01L21/8258

Abstract:
A structure and method of fabricating a semiconductor field-effect transistor (MOSFET) such as a strained Si n-MOSFET where dislocation or crystal defects spanning from source to drain is partially occupied by heavy p-type dopants. Preferably, the strained-layer n-MOSFET includes a Si, SiGe or SiGeC multi-layer structure having, in the region between source and drain, impurity atoms that preferentially occupy the dislocation sites so as to prevent shorting of source and drain via dopant diffusion along the dislocation. Advantageously, devices formed as a result of the invention are immune to dislocation-related failures, and therefore are more robust to processing and material variations. The invention thus relaxes the requirement for reducing the threading dislocation density in SiGe buffers, since the devices will be operable despite the presence of a finite number of dislocations.
Public/Granted literature
- US20090325358A1 METHOD OF REDUCING DISLOCATION-INDUCED LEAKAGE IN A STRAINED-LAYER FIELD-EFFECT TRANSISTOR Public/Granted day:2009-12-31
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