Invention Grant
- Patent Title: Method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning
- Patent Title (中): 利用自对准双重图案化制造半导体器件精细图案的方法
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Application No.: US12717923Application Date: 2010-03-04
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Publication No.: US08343871B2Publication Date: 2013-01-01
- Inventor: Tah-Te Shih , Chung-Yuan Lee
- Applicant: Tah-Te Shih , Chung-Yuan Lee
- Applicant Address: TW Hwa-Ya Technology Park Kueishan, Taoyuan
- Assignee: Inotera Memories, Inc.
- Current Assignee: Inotera Memories, Inc.
- Current Assignee Address: TW Hwa-Ya Technology Park Kueishan, Taoyuan
- Agent Winston Hsu; Scott Margo
- Priority: TW98146610A 20091231
- Main IPC: H01L21/302
- IPC: H01L21/302
Abstract:
A method for making a semiconductor device includes forming a first mask pattern on a device layer, forming a second mask pattern on the first mask pattern, etching the device layer not covered by the first and second mask patterns to thereby form a first trench, trimming the first mask pattern to form an intermediate mask pattern, depositing a material layer to fill the first trench, polishing the material layer to expose a top surface of the intermediate mask pattern, removing the intermediate mask pattern to form an opening, etching the device layer through the opening to thereby form a second trench.
Public/Granted literature
- US20110159691A1 METHOD FOR FABRICATING FINE PATTERNS OF SEMICONDUCTOR DEVICE UTILIZING SELF-ALIGNED DOUBLE PATTERNING Public/Granted day:2011-06-30
Information query
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