Invention Grant
US08343875B2 Methods of forming an integrated circuit with self-aligned trench formation
有权
形成具有自对准沟槽形成的集成电路的方法
- Patent Title: Methods of forming an integrated circuit with self-aligned trench formation
- Patent Title (中): 形成具有自对准沟槽形成的集成电路的方法
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Application No.: US13347478Application Date: 2012-01-10
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Publication No.: US08343875B2Publication Date: 2013-01-01
- Inventor: Werner Juengling , Richard Lane
- Applicant: Werner Juengling , Richard Lane
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Knobbe, Martens, Olson & Bear, LLP
- Main IPC: H01L21/3105
- IPC: H01L21/3105
Abstract:
Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set of trenches. Methods taught herein can be used as a pitch doubling technique, and may therefore enhance device integration. Further, employing a very thin CMP stop layer, and recessing surrounding materials by about an equal amount to the thickness of the CMP stop layer, provides improved planarity at the surface of the device.
Public/Granted literature
- US20120108069A1 METHODS OF FORMING AN INTEGRATED CIRCUIT WITH SELF-ALIGNED TRENCH FORMATION Public/Granted day:2012-05-03
Information query
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