Invention Grant
- Patent Title: Low voltage diode with reduced parasitic resistance and method for fabricating
- Patent Title (中): 降低寄生电阻的低压二极管和制造方法
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Application No.: US12905374Application Date: 2010-10-15
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Publication No.: US08344398B2Publication Date: 2013-01-01
- Inventor: Primit Parikh , Sten Heikman
- Applicant: Primit Parikh , Sten Heikman
- Applicant Address: US CA Goleta
- Assignee: Cree, Inc.
- Current Assignee: Cree, Inc.
- Current Assignee Address: US CA Goleta
- Agency: Koppel, Patrick, Heybl & Philpott
- Main IPC: H01L33/00
- IPC: H01L33/00

Abstract:
A method of making a diode begins by depositing an AlxGa1-xN nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n− GaN layer, an AlxGa1-xN barrier layer, and an SiO2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au—Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n−, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal, and an ohmic contact is deposited on the n+ layer.
Public/Granted literature
- US20110031579A1 LOW VOLTAGE DIODE WITH REDUCED PARASITIC RESISTANCE AND METHOD FOR FABRICATING Public/Granted day:2011-02-10
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