Invention Grant
US08344418B2 Materials for interfacing high-K dielectric layers with III-V semiconductors
有权
用于将高K电介质层与III-V半导体接口的材料
- Patent Title: Materials for interfacing high-K dielectric layers with III-V semiconductors
- Patent Title (中): 用于将高K电介质层与III-V半导体接口的材料
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Application No.: US12646436Application Date: 2009-12-23
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Publication No.: US08344418B2Publication Date: 2013-01-01
- Inventor: Willy Rachmady , Marko Radosavljevic , Gilbert Dewey , Robert S. Chau
- Applicant: Willy Rachmady , Marko Radosavljevic , Gilbert Dewey , Robert S. Chau
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L31/102
- IPC: H01L31/102

Abstract:
A group III chalcogenide layer for interfacing a high-k dielectric to a III-V semiconductor surface and methods of forming the same. A III-V QWFET includes a gate stack which comprises a high-K gate dielectric layer disposed on an interfacial layer comprising a group III chalcogenide. In an embodiment, a III-V semiconductor surface comprising a native oxide is sequentially exposed to TMA and H2S provided in an ALD process to remove substantially all the native oxide and form an Al2S3 layer on the semiconductor surface.
Public/Granted literature
- US20110147795A1 MATERIALS FOR INTERFACING HIGH-K DIELECTRIC LAYERS WITH III-V SEMICONDUCTORS Public/Granted day:2011-06-23
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