Invention Grant
- Patent Title: Semiconductor device
- Patent Title (中): 半导体器件
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Application No.: US13048926Application Date: 2011-03-16
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Publication No.: US08344454B2Publication Date: 2013-01-01
- Inventor: Kyoya Nitta , Yutaka Hoshino
- Applicant: Kyoya Nitta , Yutaka Hoshino
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Mattingly & Malur, PC
- Priority: JP2010-090752 20100409
- Main IPC: H01L27/12
- IPC: H01L27/12

Abstract:
An object of the invention is to provide a semiconductor device having improved performance, high reliability, and a reduced chip size, in particular, to provide a semiconductor device having an MOSFET over an SOI substrate capable of maintaining its reliability while controlling the potential of a well below a gate electrode and preventing generation of parasitic capacitance. Generation of parasitic capacitance is prevented by controlling the potential of a well below a gate electrode by using a well contact plug passing through a hole portion formed in a gate electrode wiring. Generation of defects in a gate insulating film is prevented by making use of a gettering effect produced by causing an element isolation region to extend along the gate electrode.
Public/Granted literature
- US20110248344A1 SEMICONDUCTOR DEVICE Public/Granted day:2011-10-13
Information query
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