Invention Grant
- Patent Title: Wafer level packaging of semiconductor chips
- Patent Title (中): 晶圆级封装半导体芯片
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Application No.: US11847101Application Date: 2007-08-29
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Publication No.: US08344505B2Publication Date: 2013-01-01
- Inventor: Neil Mclellan , Adam Zbrzezny
- Applicant: Neil Mclellan , Adam Zbrzezny
- Applicant Address: CA Markham, Ontario
- Assignee: ATI Technologies ULC
- Current Assignee: ATI Technologies ULC
- Current Assignee Address: CA Markham, Ontario
- Agency: Faegre Baker Daniels LLP
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads.
Public/Granted literature
- US20090057887A1 WAFER LEVEL PACKAGING OF SEMICONDUCTOR CHIPS Public/Granted day:2009-03-05
Information query
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