Invention Grant
- Patent Title: Apparatus for stacking integrated circuits
- Patent Title (中): 用于堆叠集成电路的装置
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Application No.: US12828175Application Date: 2010-06-30
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Publication No.: US08344518B2Publication Date: 2013-01-01
- Inventor: Mark Moshayedi
- Applicant: Mark Moshayedi
- Applicant Address: US CA Santa Ana
- Assignee: STEC, Inc.
- Current Assignee: STEC, Inc.
- Current Assignee Address: US CA Santa Ana
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L23/52
- IPC: H01L23/52

Abstract:
A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack.
Public/Granted literature
- US20100327436A1 APPARATUS AND METHOD FOR STACKING INTEGRATED CIRCUITS Public/Granted day:2010-12-30
Information query
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