Invention Grant
- Patent Title: LDO linear regulator with improved transient response
- Patent Title (中): LDO线性稳压器具有改善的瞬态响应
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Application No.: US13004044Application Date: 2011-01-11
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Publication No.: US08344713B2Publication Date: 2013-01-01
- Inventor: Mithlesh Shrivas , Mayank Jain
- Applicant: Mithlesh Shrivas , Mayank Jain
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Charles Bergere
- Main IPC: G05F1/56
- IPC: G05F1/56

Abstract:
An LDO regulator system has first and second current mirror circuits connected to its output terminal. A load attached to the output terminal is supplied with a constant voltage. Variations in the load that cause variations in the magnitude of the output voltage trigger one of the first or second current mirror circuits to generate a current that varies the magnitude of a gate voltage of a pass-transistor. The variation in the gate voltage in turns varies the drain current of the pass-transistor, which varies the output voltage to counter the change in the magnitude of the output voltage. Using the first and second current mirror circuits avoids the need for a large load capacitor and very high bandwidth of a conventional LDO regulator.
Public/Granted literature
- US20120176107A1 LDO LINEAR REGULATOR WITH IMPROVED TRANSIENT RESPONSE Public/Granted day:2012-07-12
Information query
IPC分类: