Invention Grant
- Patent Title: Jitter suppression circuit and jitter suppression method
- Patent Title (中): 抖动抑制电路和抖动抑制方法
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Application No.: US12672619Application Date: 2008-09-04
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Publication No.: US08344769B2Publication Date: 2013-01-01
- Inventor: Takahiro Adachi
- Applicant: Takahiro Adachi
- Applicant Address: JP Tokyo
- Assignee: NEC Corporation
- Current Assignee: NEC Corporation
- Current Assignee Address: JP Tokyo
- Priority: JP2007-236563 20070912
- International Application: PCT/JP2008/066001 WO 20080904
- International Announcement: WO2009/034917 WO 20090319
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
There is provided a jitter suppression circuit and a jitter suppression method in which both shortening of a pull-in time and high jitter suppression characteristics is satisfied. In a jitter suppression circuit using a digital phase locked loop, both shortening of a pull-in time and high jitter suppression effect can be satisfied by determining whether the loop is in a synchronous state or not using a phase difference between an input clock and an output clock, and changing characteristics of a loop filter by the determination result.
Public/Granted literature
- US20110193602A1 JITTER SUPPRESSION CIRCUIT AND JITTER SUPPRESSION METHOD Public/Granted day:2011-08-11
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