Invention Grant
US08344773B2 Clock generating circuit, semiconductor device including the same, and data processing system
有权
时钟发生电路，包括它的半导体器件和数据处理系统
- Patent Title: Clock generating circuit, semiconductor device including the same, and data processing system
- Patent Title (中): 时钟发生电路，包括它的半导体器件和数据处理系统
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Application No.: US13360576Application Date: 2012-01-27
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Publication No.: US08344773B2Publication Date: 2013-01-01
- Inventor: Kazutaka Miyano
- Applicant: Kazutaka Miyano
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2009-207401 20090908
- Main IPC: H03L7/06
- IPC: H03L7/06
Abstract:
A semiconductor device includes a delay circuit supplied with a first clock signal and a first phase determination signal and producing a second clock signal, the delay circuit controlling the second clock signal such that a delay in phase of the second clock signal to the first clock signal is increased when the first phase determination signal takes a first logic level and decreased when the first phase determination signal takes a second logic level, and a phase determining circuit supplied with the first clock signal and a third clock signal, which is produced in response to the second clock signal, and producing a second phase determination signal in response to a difference in phase between the first clock signal and the third clock signal.
Public/Granted literature
- US20120134223A1 CLOCK GENERATING CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM Public/Granted day:2012-05-31
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