Invention Grant
US08344921B2 Sigma-delta modulator with SAR ADC and truncater having order lower than order of integrator and related sigma-delta modulation method 有权
具有SAR ADC和截断器的Σ-Δ调制器具有低于积分器的阶数和相关的Σ-Δ调制方法

  • Patent Title: Sigma-delta modulator with SAR ADC and truncater having order lower than order of integrator and related sigma-delta modulation method
  • Patent Title (中): 具有SAR ADC和截断器的Σ-Δ调制器具有低于积分器的阶数和相关的Σ-Δ调制方法
  • Application No.: US13072797
    Application Date: 2011-03-28
  • Publication No.: US08344921B2
    Publication Date: 2013-01-01
  • Inventor: Yu-Hsin LinHung-Chieh TsaiSheng-Jui Huang
  • Applicant: Yu-Hsin LinHung-Chieh TsaiSheng-Jui Huang
  • Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
  • Assignee: Mediatek Inc.
  • Current Assignee: Mediatek Inc.
  • Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
  • Agent Winston Hsu; Scott Margo
  • Main IPC: H03M3/00
  • IPC: H03M3/00
Sigma-delta modulator with SAR ADC and truncater having order lower than order of integrator and related sigma-delta modulation method
Abstract:
A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information, wherein an order of the truncater is lower than an order of the integration.
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