Invention Grant
- Patent Title: Semiconductor device
- Patent Title (中): 半导体器件
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Application No.: US13293194Application Date: 2011-11-10
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Publication No.: US08345458B2Publication Date: 2013-01-01
- Inventor: Masaki Shiraishi , Noboru Akiyama , Tomoaki Uno , Nobuyoshi Matsuura
- Applicant: Masaki Shiraishi , Noboru Akiyama , Tomoaki Uno , Nobuyoshi Matsuura
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP2004-345798 20041130
- Main IPC: H02M1/10
- IPC: H02M1/10 ; H01L23/48 ; H05K7/02

Abstract:
In order to reduce parasitic inductance of a main circuit in a power supply circuit, a non-insulated DC-DC converter is provided having a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.
Public/Granted literature
- US20120049290A1 SEMICONDUCTOR DEVICE Public/Granted day:2012-03-01
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