The present disclosure includes systems and techniques relating to non-volatile memory. A described systems, for example, includes a non-volatile memory structure that includes memory cells configured to store information based on four or more charge levels associated with four or more states respectively. The four or more states can be indicative of information that includes first bit information in a first bit position and second bit information in a second bit position. The described system includes a controller configured to use at least one of four or more programming voltages associated with the four or more states, respectively, to affect a charge of a memory cell. The programming voltages can be selected to reduce differences among bit error rates of individual bit positions in a state determined by reading a charge of a memory cell.