Invention Grant
US08345481B2 NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array
失效
基于NAND的NMOS NOR闪存单元,基于NAND的NMOS NOR闪存阵列,以及形成基于NAND的NMOS NOR闪存阵列的方法
- Patent Title: NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array
- Patent Title (中): 基于NAND的NMOS NOR闪存单元,基于NAND的NMOS NOR闪存阵列,以及形成基于NAND的NMOS NOR闪存阵列的方法
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Application No.: US13317678Application Date: 2011-10-25
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Publication No.: US08345481B2Publication Date: 2013-01-01
- Inventor: Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
- Applicant: Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
- Applicant Address: US CA San Jose
- Assignee: Aplus Flash Technology, Inc.
- Current Assignee: Aplus Flash Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman; Billy Knowles
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
A NOR flash nonvolatile memory or reconfigurable logic device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.
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