Invention Grant
- Patent Title: Erase ramp pulse width control for non-volatile memory
- Patent Title (中): 擦除非易失性存储器的斜坡脉冲宽度控制
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Application No.: US13023713Application Date: 2011-02-09
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Publication No.: US08345485B2Publication Date: 2013-01-01
- Inventor: Jon S. Choy , Chen He
- Applicant: Jon S. Choy , Chen He
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Gary Stanford
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
A method of erasing a memory block of a non-volatile memory, including setting a pulse width of erase pulses to an initial width, repeatedly applying erase pulses to the memory block until the memory block meets an erase metric or until a maximum number of erase pulses have been applied, gradually adjusting a pulse voltage magnitude of the erase pulses from an initial pulse voltage level to a maximum pulse voltage level, and reducing the width of the erase pulses to less than the initial width when the pulse voltage magnitude reaches an intermediate voltage level between the initial pulse voltage level and the maximum pulse voltage level. Thus, narrow pulses are applied at higher voltage levels to reduce the amount of over erasure of the memory block.
Public/Granted literature
- US20120201082A1 ERASE RAMP PULSE WIDTH CONTROL FOR NON-VOLATILE MEMORY Public/Granted day:2012-08-09
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