Invention Grant
- Patent Title: Booster circuit and semiconductor memory
- Patent Title (中): 加速电路和半导体存储器
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Application No.: US12892251Application Date: 2010-09-28
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Publication No.: US08345503B2Publication Date: 2013-01-01
- Inventor: Atsushi Nakakubo
- Applicant: Atsushi Nakakubo
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Fujitsu Patent Center
- Priority: JP2009-224808 20090929
- Main IPC: G11C5/14
- IPC: G11C5/14

Abstract:
A booster circuit includes a first capacitor and a second capacitor serially coupled between a first node and a second node through a third node; a third capacitor and a fourth capacitor serially coupled between a fourth node and a fifth node through a sixth node; a first switch coupling the third node with a power supply line when the fourth node is set to a first level; a second switch coupling the sixth node with the power supply line when the first node is set to the first level; a third switch transferring a plurality of electric charges of the sixth node to the second node; a fourth switch transferring a plurality of electric charges of the third node to the fifth node; a fifth switch coupling the second node with a voltage line; and a sixth switch coupling the fifth node with the voltage line.
Public/Granted literature
- US20110075487A1 BOOSTER CIRCUIT AND SEMICONDUCTOR MEMORY Public/Granted day:2011-03-31
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