Invention Grant
US08345811B2 Digital radio processor architecture with reduced DCO modulation range requirement
有权
数字无线电处理器架构具有降低的DCO调制范围要求
- Patent Title: Digital radio processor architecture with reduced DCO modulation range requirement
- Patent Title (中): 数字无线电处理器架构具有降低的DCO调制范围要求
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Application No.: US12060886Application Date: 2008-04-02
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Publication No.: US08345811B2Publication Date: 2013-01-01
- Inventor: Sarma S. Gunturi , Jawaharlal Tangudu , Sthanunathan Ramakrishnan , Jayawardan Janardhanan , Debapriya Sahu , Subhashish Mukherjee
- Applicant: Sarma S. Gunturi , Jawaharlal Tangudu , Sthanunathan Ramakrishnan , Jayawardan Janardhanan , Debapriya Sahu , Subhashish Mukherjee
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Ronald O. Neerings; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from π/2, π/4, π/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of π/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.
Public/Granted literature
- US20090252269A1 DIGITAL RADIO PROCESSOR ARCHITECTURE WITH REDUCED DCO MODULATION RANGE REQUIREMENT Public/Granted day:2009-10-08
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