Register includes flip-flop circuits each constructed to retain data of n bit in synchronism with a clock pulse, the register retaining a multiplication result of a multiplier dividedly by the flip-flop circuits, n bit per flip-flop circuit. For each of a first and second numeric value data to be multiplied by the multiplier, a control circuit detects the number of consecutive zeros from the lowest-order bit of the data and performs control, on the basis of the detected number of the consecutive zeros and for each flip-flop circuit, as to whether or not the clock pulse should be supplied to the flip-flop circuit. The control circuit obtains an integral quotient value x by dividing by the number n the sum between the detected numbers for the first and second numeric value data, to stop the clock pulse supply to a particular number x of flip-flop circuit counted from the lowest-order.