Invention Grant
- Patent Title: Device address assignment in a bus cascade system
- Patent Title (中): 总线级联系统中的设备地址分配
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Application No.: US12854041Application Date: 2010-08-10
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Publication No.: US08346977B2Publication Date: 2013-01-01
- Inventor: Xiaojun Zeng , Kaiya Sheng
- Applicant: Xiaojun Zeng , Kaiya Sheng
- Applicant Address: KY Grand Cayman
- Assignee: O2Micro International Limited
- Current Assignee: O2Micro International Limited
- Current Assignee Address: KY Grand Cayman
- Agency: SNR Denton US LLP
- Priority: CN201010179342 20100520
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F13/00

Abstract:
According to one aspect there is disclosed an apparatus. The apparatus may include a first device. The first device may include a first serial input port configured to receive serial data from at least one of a host MCU and a second device; a first serial output port configured to output the serial data to a third device when the third device is coupled to the first device; a first shift register configured to receive the serial data from the first serial input port; a first multiplexer configured to selectively couple the first serial output port to the first shift register or the first serial input port; and a bus controller configured to receive the serial data from the first serial input port, the bus controller further configured to control the first multiplexer to couple the first serial output port to the first serial input port or the first shift register, based at least in part on the serial data, wherein the serial data includes a command section of a command and at least a portion of a payload section of the command, wherein the command section includes a command code, a target address and an error check and the payload section includes at least one new address and at least one corresponding error check.
Public/Granted literature
- US20110289239A1 DEVICE ADDRESS ASSIGNMENT IN A BUS CASCADE SYSTEM Public/Granted day:2011-11-24
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