Invention Grant
US08347034B1 Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access
有权
透明的2级缓存，使用独立的标签和有效的随机存取存储器阵列进行缓存访问
- Patent Title: Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access
- Patent Title (中): 透明的2级缓存，使用独立的标签和有效的随机存取存储器阵列进行缓存访问
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Application No.: US11034846Application Date: 2005-01-13
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Publication No.: US08347034B1Publication Date: 2013-01-01
- Inventor: Hong-Yi Chen , Geoffrey K. Yung
- Applicant: Hong-Yi Chen , Geoffrey K. Yung
- Applicant Address: BM Hamilton
- Assignee: Marvell International Ltd.
- Current Assignee: Marvell International Ltd.
- Current Assignee Address: BM Hamilton
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00
Abstract:
A computer cache for a memory comprises a data random-access memory (RAM) containing a plurality of cache lines. Each of the cache lines stores a segment of the memory. A tag RAM contains a plurality of address tags that correspond to the cache lines. A valid RAM contains a plurality of validity values that correspond to the cache lines. The valid RAM is stored separately from the tag RAM and the data RAM. The valid RAM is selectively independently clearable. A hit module determines whether data is stored in the computer cache based upon the valid RAM and the tag RAM.
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