Invention Grant
US08347040B2 Latency reduction for cache coherent bus-based cache 有权
缓存相关总线缓存的延迟降低

Latency reduction for cache coherent bus-based cache
Abstract:
In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.
Public/Granted literature
Information query
Patent Agency Ranking
0/0