Invention Grant
- Patent Title: Latency reduction for cache coherent bus-based cache
- Patent Title (中): 缓存相关总线缓存的延迟降低
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Application No.: US13089050Application Date: 2011-04-18
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Publication No.: US08347040B2Publication Date: 2013-01-01
- Inventor: Brian P. Lilly , Sridhar P. Subramanian , Ramesh Gunna
- Applicant: Brian P. Lilly , Sridhar P. Subramanian , Ramesh Gunna
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Agent Lawrence J. Merkel
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.
Public/Granted literature
- US20110197030A1 Latency Reduction for Cache Coherent Bus-Based Cache Public/Granted day:2011-08-11
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