Invention Grant
- Patent Title: Fast lithography compliance check for place and route optimization
- Patent Title (中): 快速光刻符合性检查地点和路线优化
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Application No.: US11479422Application Date: 2006-06-30
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Publication No.: US08347239B2Publication Date: 2013-01-01
- Inventor: Alexander Miloslavsky , Gerard Lukpat
- Applicant: Alexander Miloslavsky , Gerard Lukpat
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A computer is programmed to use at least one rule to identify from within a layout of an IC design, a set of regions likely to fail if fabricated unchanged. An example of such a rule of detection is to check for presence of two neighbors neither of which fully overlaps a short wire or an end of a long wire. The computer uses at least another rule to change at least one region in the set of regions, to obtain a second layout which is less likely to fail in the identified regions. An example of such a rule of correction is to elongate at least one of the two neighbors. The computer may perform optical rule checking (ORC) in any order relative to application of the rules, e.g. ORC can be performed between detection rules and correction rules i.e. performed individually on each identified region prior to correction.
Public/Granted literature
- US20080005704A1 Fast lithography compliance check for place and route optimization Public/Granted day:2008-01-03
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