A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.