Invention Grant
- Patent Title: Integrated circuit and manufacturing process facilitating selective configuration for electromagnetic compatibility
- Patent Title (中): 集成电路和制造过程便于电磁兼容性的选择性配置
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Application No.: US11967880Application Date: 2007-12-31
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Publication No.: US08347251B2Publication Date: 2013-01-01
- Inventor: Paul Paternoster , Vaibhavi Sabharanjak , Po-Shen Lai
- Applicant: Paul Paternoster , Vaibhavi Sabharanjak , Po-Shen Lai
- Applicant Address: US CA Milpitas
- Assignee: SanDisk Corporation
- Current Assignee: SanDisk Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Patterson, Thuente Christensen Pendersen PA
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
An integrated circuit (IC) having a selectively-designated electromagnetic compatibility (EMC) performance characteristic. The IC includes an IC die having an input or output (I/O) node. A first I/O cell of a first type associated with the I/O node provides a first EMC performance characteristic, and a second I/O cell of a second type associated with the I/O node provides a second EMC performance characteristic different from the first EMC performance characteristic. A first bonding pad is electrically coupled with the first I/O cell, and a second bonding pad is electrically coupled with the second I/O cell. The IC die can be packaged into a packaged IC having an I/O pin corresponding to the I/O node. The I/O pin is wired to one of either the first bonding pad or the second bonding pad, but not to the other, such that a pinout for the I/O node is preferentially provided having one of either the first EMC performance characteristic or the second EMC performance characteristic.
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