Invention Grant
- Patent Title: Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array
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Application No.: US12510938Application Date: 2009-07-28
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Publication No.: US08347252B2Publication Date: 2013-01-01
- Inventor: Victor Moroz , Dipankar Pramanik
- Applicant: Victor Moroz , Dipankar Pramanik
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Kenta Suzue
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations.
Public/Granted literature
- US20090288049A1 Method for Rapid Estimation of Layout-Dependent Threshold Voltage Variation in a MOSFET Array Public/Granted day:2009-11-19
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