Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry

Invention Grant

US08349699B2 Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry 有权

Title translation: 在集成电路的制造中形成沟槽隔离的方法和制造集成电路的方法

Please log in to see more content

Patent Title: Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry
Patent Title (中): 在集成电路的制造中形成沟槽隔离的方法和制造集成电路的方法
Application No.: US13211174

Application Date: 2011-08-16
Publication No.: US08349699B2

Publication Date: 2013-01-08
Inventor: Robert D. Patraw , Martin Ceredig Roberts , Keith R. Cook
Applicant: Robert D. Patraw , Martin Ceredig Roberts , Keith R. Cook
Applicant Address: US ID Boise
Assignee: Micron Technology, Inc.
Current Assignee: Micron Technology, Inc.
Current Assignee Address: US ID Boise
Agency: Wells St. John P.S.
Main IPC: H01L21/76
IPC: H01L21/76

Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry

Abstract:

First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material. The spin-on-dielectric is densified within the second isolation trench.

Abstract(Chinese):

第一和第二隔离沟槽形成半导体衬底的半导体材料。第一隔离沟槽具有比第二隔离沟槽小的最小横截面尺寸。绝缘层沉积在第一和第二隔离沟槽内，有效地填充半导体材料内的第一隔离沟槽的剩余容积，而不是半导体材料内的第二隔离沟槽的剩余体积。绝缘层包括从流动TEOS沉积到第一和第二隔离沟槽的二氧化硅。通过在半导体材料内的第二隔离沟槽内流动TEOS，而不是在半导体材料内的第一隔离沟槽内，在沉积的二氧化硅上沉积自旋电介质。沉积电介质有效地填充半导体材料内的第二隔离沟槽的剩余体积。旋转电介质在第二隔离沟槽内致密化。

Public/Granted literature

US20110300689A1 Methods of Forming Trench Isolation in the Fabrication of Integrated Circuitry and Methods of Fabricating Integrated Circuitry Public/Granted day:2011-12-08

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/71	..限定在组H01L21／70中的器件的特殊部件的制造（H01L21/28，H01L21/44，H01L21/48优先）
H01L21/76	...组件间隔离区的制作