Invention Grant
US08354300B2 Reducing susceptibility to electrostatic discharge damage during die-to-die bonding for 3-D packaged integrated circuits
有权
降低了针对3-D封装集成电路的管芯到芯片之间的静电放电损坏的敏感性
- Patent Title: Reducing susceptibility to electrostatic discharge damage during die-to-die bonding for 3-D packaged integrated circuits
- Patent Title (中): 降低了针对3-D封装集成电路的管芯到芯片之间的静电放电损坏的敏感性
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Application No.: US12710586Application Date: 2010-02-23
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Publication No.: US08354300B2Publication Date: 2013-01-15
- Inventor: Brian Matthew Henderson , Arvind Chandrasekaran
- Applicant: Brian Matthew Henderson , Arvind Chandrasekaran
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Michelle Gallardo; Nicholas J. Pauley; Jonathan T. Velasco
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/02
Abstract:
Mitigating electrostatic discharge damage when fabricating a 3-D integrated circuit package, wherein in one embodiment when a second tier die is placed in contact with a first tier die, conductive bumps near the perimeter of the second tier die that are electrically coupled to the substrate of the second tier die make contact with corresponding conductive bumps on the first tier die that are electrically coupled to the substrate of first tier die before other signal conductive bumps and power conductive bumps on the second tier and first tier dice make electrical contact.
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Information query
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