Invention Grant
- Patent Title: Non-volatile NAND memory semiconductor integrated circuit
- Patent Title (中): 非易失性NAND存储器半导体集成电路
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Application No.: US13164950Application Date: 2011-06-21
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Publication No.: US08354705B2Publication Date: 2013-01-15
- Inventor: Toshitake Yaegashi , Yoshio Ozawa
- Applicant: Toshitake Yaegashi , Yoshio Ozawa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2004-242558 20040823
- Main IPC: H01L29/778
- IPC: H01L29/778 ; H01L21/336

Abstract:
A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating film which is formed on the first insulating film and does not contain nitrogen as a main component, and a third insulating film formed on the first diffusion layers, first gate electrodes, second diffusion layers and second gate electrodes with the second insulating film disposed therebetween in a partial region. The second insulating film is formed to fill the concave portions and a portion between the first and second gate electrodes has a multi-layered structure containing at least the first and second insulating films.
Public/Granted literature
- US20110248330A1 METHOD OF MANUFACTURING A NON-VOLATILE NAND MEMORY SEMICONDUCTOR INTEGRATED CIRCUIT Public/Granted day:2011-10-13
Information query
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