Invention Grant
- Patent Title: Method of fabricating semiconductor device
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Application No.: US13107542Application Date: 2011-05-13
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Publication No.: US08354713B2Publication Date: 2013-01-15
- Inventor: Sumito Numazawa , Yoshito Nakazawa , Masayoshi Kobayashi , Satoshi Kudo , Yasuo Imai , Sakae Kubo , Takashi Shigematsu , Akihiro Ohnishi , Kozo Uesawa , Kentaro Oishi
- Applicant: Sumito Numazawa , Yoshito Nakazawa , Masayoshi Kobayashi , Satoshi Kudo , Yasuo Imai , Sakae Kubo , Takashi Shigematsu , Akihiro Ohnishi , Kozo Uesawa , Kentaro Oishi
- Applicant Address: JP Kanagawa JP Tokyo
- Assignee: Renesas Electronics Corporation,Hitachi ULSI Systems Co., Ltd.
- Current Assignee: Renesas Electronics Corporation,Hitachi ULSI Systems Co., Ltd.
- Current Assignee Address: JP Kanagawa JP Tokyo
- Agency: Mattingly & Malur, PC
- Priority: JP9-232425 19970828
- Main IPC: H01L29/66
- IPC: H01L29/66

Abstract:
In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
Public/Granted literature
- US20110215398A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE Public/Granted day:2011-09-08
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