Invention Grant
US08354714B2 SOI MOS device having BTS structure and manufacturing method thereof
有权
具有BTS结构的SOI MOS器件及其制造方法
- Patent Title: SOI MOS device having BTS structure and manufacturing method thereof
- Patent Title (中): 具有BTS结构的SOI MOS器件及其制造方法
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Application No.: US13132879Application Date: 2010-09-07
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Publication No.: US08354714B2Publication Date: 2013-01-15
- Inventor: Jing Chen , Jiexin Luo , Qingqing Wu , Xiaolu Huang , Xi Wang
- Applicant: Jing Chen , Jiexin Luo , Qingqing Wu , Xiaolu Huang , Xi Wang
- Applicant Address: CN Changning District, Shanghai
- Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
- Current Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
- Current Assignee Address: CN Changning District, Shanghai
- Agency: Global IP Services
- Agent Tianhua Gu
- Priority: CN201010225623 20100713
- International Application: PCT/CN2010/076678 WO 20100907
- International Announcement: WO2012/006805 WO 20120119
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L31/062

Abstract:
The present invention discloses a SOI MOS device having BTS structure and manufacturing method thereof. The source region of the SOI MOS device comprises: two heavily doped N-type regions, a heavily doped P-type region formed between the two heavily doped N-type regions, a silicide formed above the heavily doped N-type regions and the heavily doped P-type region, and a shallow N-type region which is contact to the silicide; an ohmic contact is formed between the heavily doped P-type region and the silicide thereon to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof without increasing the chip area and also overcome the disadvantages such as decreased effective channel width of the devices in the BTS structure of the prior art. The manufacturing method comprises steps of: forming a heavily doped P-type region via ion implantation, forming a metal layer above the source region and forming a silicide via the heat treatment between the metal layer and the Si underneath. The device in the present invention could be fabricated via simplified fabricating process with great compatibility with traditional CMOS technology.
Public/Granted literature
- US20120012931A1 SOI MOS DEVICE HAVING BTS STRUCTURE AND MANUFACTURING METHOD THEREOF Public/Granted day:2012-01-19
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