Invention Grant
US08354736B2 Reclaiming usable integrated circuit chip area near through-silicon vias
有权
回收通过硅通孔的可用集成电路芯片区域
- Patent Title: Reclaiming usable integrated circuit chip area near through-silicon vias
- Patent Title (中): 回收通过硅通孔的可用集成电路芯片区域
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Application No.: US12687358Application Date: 2010-01-14
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Publication No.: US08354736B2Publication Date: 2013-01-15
- Inventor: Victor Moroz
- Applicant: Victor Moroz
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Warren S. Wolfeld
- Main IPC: H01L29/40
- IPC: H01L29/40

Abstract:
Roughly described, an integrated circuit device includes a substrate including a via passing therethrough, a strained electrically conductive first material in the via, the first material tending to introduce first stresses into the substrate, and a strained second material in the via, the second material tending to introduce second stresses into the substrate which at least partially cancel the first stresses. In an embodiment, SiGe is grown epitaxially on the inside sidewall of the via in the silicon wafer. SiO2 is then formed on the inside surface of the SiGe, and metal is formed down the center. The stresses introduce by the SiGe tend to counteract the stresses introduced by the metal, thereby reducing or eliminating undesirable stress in the silicon and permitting the placement of transistors in close proximity to the TSV.
Public/Granted literature
- US20110169140A1 RECLAIMING USABLE INTEGRATED CIRCUIT CHIP AREA NEAR THROUGH-SILICON VIAS Public/Granted day:2011-07-14
Information query
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