A layer assemblage for a semiconductor chip having a chip body for producing a soldering connection for the chip. The assemblage is provided on a side of a chip body formed from a semiconducting material, wherein the layer assemblage is formed from a plurality of sequential metal layers which follow one above another and are produced by means of a physical coating method, and wherein a solderable soldering layer is provided between a noble metal layer situated at a surface of the layer assemblage and the chip body. In order to avoid an undesired penetration of a solder through the layer assemblage the soldering layer has at least one internal interface formed by an interruption of the coating method.