Invention Grant
- Patent Title: Phase-locked loop circuit and an associated method
- Patent Title (中): 锁相环电路及相关方法
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Application No.: US12718291Application Date: 2010-03-05
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Publication No.: US08354867B2Publication Date: 2013-01-15
- Inventor: Shey-Shi Lu , Hsien-Ku Chen
- Applicant: Shey-Shi Lu , Hsien-Ku Chen
- Applicant Address: TW Taipei
- Assignee: National Taiwan University
- Current Assignee: National Taiwan University
- Current Assignee Address: TW Taipei
- Agency: Morris Manning & Martin LLP
- Agent Tim Tingkang Xia, Esq.
- Priority: TW98107231A 20090306
- Main IPC: H03D9/00
- IPC: H03D9/00 ; G01R25/00 ; H03L7/06 ; H03L7/00
Abstract:
The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider.
Public/Granted literature
- US20100225368A1 PHASE-LOCKED LOOP CIRCUIT AND AN ASSOCIATED METHOD Public/Granted day:2010-09-09
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