Method and system for aligning a clock signal to parallel data are described. According to one embodiment, a clock shifting circuit shifts an incoming clock signal relative to an incoming data signal, and a data clocking circuit uses the shifted clock signal to reclock the incoming data signal. The clock shifting circuit may comprise a phase locked loop (PLL) coupled with multiple D flip flops (DFFs) connected in series. Divisional combinatorial logic may be disposed between DFFs in the series. Data clocking circuits may comprise one DFF to reclock each incoming data bit, a pair of DFFs to reclock each incoming data bit, or other circuits such as true-complement blocks to serve as local oscillators to mixers. Multiple shifted clock signals may be produced, such as those shifted 60, 90, 120, 180, 240, and 270 degrees relative to the incoming clock signal.