An architecture verifying apparatus includes an input unit receiving a time limit of a semiconductor integrated circuit including modules and buses, and performance specifications of the modules, a bus monitor acquiring bus transactions issued to the buses by the modules, a module monitor acquiring input transactions used when the module inputs data, processing information indicating processing contents and processing time used when the module processes the data, and output transactions used when the module outputs the processed data, a first architecture generator associating the processing information with the bus transaction, the input transaction, the processing information, and the output transaction, to generate a first architecture fulfilling the time limit, a second architecture generator changing the processing time of the first architecture, to generate a second architecture fulfilling the time limit and having power consumption lower than power consumption of the first architecture, and an output unit outputting the second architecture.