Invention Grant
- Patent Title: Method of forming electronic circuit
- Patent Title (中): 电子电路形成方法
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Application No.: US13141753Application Date: 2009-12-22
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Publication No.: US08357307B2Publication Date: 2013-01-22
- Inventor: Keisuke Yamanishi , Kengo Kaminaga , Ryo Fukuchi
- Applicant: Keisuke Yamanishi , Kengo Kaminaga , Ryo Fukuchi
- Applicant Address: JP Tokyo
- Assignee: JX Nippon Mining & Metals Corporation
- Current Assignee: JX Nippon Mining & Metals Corporation
- Current Assignee Address: JP Tokyo
- Agency: Howson & Howson LLP
- Priority: JP2008-334474 20081226
- International Application: PCT/JP2009/071283 WO 20091222
- International Announcement: WO2010/074054 WO 20100701
- Main IPC: H01B13/00
- IPC: H01B13/00

Abstract:
Provided is a method of forming an electronic circuit, wherein a nickel or nickel alloy layer is formed on an etching side of a rolled copper foil or an electrolytic copper foil, the rolled copper foil or the electrolytic copper foil is bonded to a resin substrate to obtain a copper-clad laminate, a resist pattern for forming a circuit is subsequently applied on the copper foil, any unwanted portion of the copper foil and the nickel or nickel alloy layer of the copper-clad laminate other than the portion to which the resist pattern was applied is removed using an etching solution of an aqueous ferric chloride, the resist is further removed, and soft etching is additionally performed in order to remove the remnant nickel or nickel alloy layer and thereby form a circuit in which the space between copper circuit lines is of a width that is double or more from the thickness of copper. This invention aims to form a circuit with a uniform circuit width, improve the etching properties in pattern etching, and prevent the occurrence of short circuits and defects in the circuit width.
Public/Granted literature
- US20110284496A1 Method of Forming Electronic Circuit Public/Granted day:2011-11-24
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