Invention Grant
US08357610B2 Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics
有权
通过减少沟槽电介质的污染,减少具有低k材料的金属化层堆叠中的沟槽的图案变化
- Patent Title: Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics
- Patent Title (中): 通过减少沟槽电介质的污染,减少具有低k材料的金属化层堆叠中的沟槽的图案变化
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Application No.: US12355112Application Date: 2009-01-16
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Publication No.: US08357610B2Publication Date: 2013-01-22
- Inventor: Frank Feustel , Thomas Werner , Michael Grillberger , Kai Frohberg
- Applicant: Frank Feustel , Thomas Werner , Michael Grillberger , Kai Frohberg
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams, Morgan & Amerson, P.C.
- Priority: DE102008016424 20080331
- Main IPC: H01L21/308
- IPC: H01L21/308 ; H01L21/768

Abstract:
By forming a protection layer prior to the application of the planarization layer during a dual damascene strategy for first patterning vias and then trenches, enhanced etch fidelity may be accomplished. In other aspects disclosed herein, via openings and trenches may be patterned in separate steps, which may be accomplished by different etch behaviors of respective dielectric materials and/or the provision of an appropriate etch stop layer, while filling the via opening and the trench with a barrier material and a highly conductive metal may be achieved in a common fill sequence. Hence, the via opening may be formed on the basis of a reduced aspect ratio, while nevertheless providing a highly efficient overall process sequence.
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