Invention Grant
- Patent Title: Method for manufacturing semiconductor device and semiconductor device
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Application No.: US12458198Application Date: 2009-07-02
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Publication No.: US08357612B2Publication Date: 2013-01-22
- Inventor: Hiroyuki Hoshizaki , Hidetaka Natsume
- Applicant: Hiroyuki Hoshizaki , Hidetaka Natsume
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-176062 20080704
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/4763

Abstract:
A semiconductor device in which a conductor of a bit line may be made as large in thickness as possible to reduce resistance of the bit line and to reduce capacitance across the neighboring bit lines. The device includes a first interlayer film having a first contact metal part accommodated in it, and a second interlayer film. The second interlayer film includes a trench, and is deposited on the first interlayer film. The semiconductor device also includes a metal conductor filled in and protruding above the trench, and a hard mask film deposited on the metal conductor. The semiconductor device also includes sidewalls formed on lateral surfaces of the hard mask film and the metal conductor for overlying the second interlayer film, and a third interlayer film formed above the second interlayer film inclusive of the hard mask film and the sidewalls. The device also includes a contact hole opened through the third interlayer film and the second interlayer film and in the first interlayer film to expose the first contact metal part between the sidewalls. The device further includes a second contact metal part 1 in the contact hole.
Public/Granted literature
- US20090273089A1 Method for manufacturing semiconductor device and semiconductor device Public/Granted day:2009-11-05
Information query
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