Invention Grant
- Patent Title: Multi-level charge storage transistors and associated methods
- Patent Title (中): 多级电荷存储晶体管及相关方法
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Application No.: US12757727Application Date: 2010-04-09
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Publication No.: US08357970B2Publication Date: 2013-01-22
- Inventor: Gurtej S. Sandhu , Nirmal Ramaswamy
- Applicant: Gurtej S. Sandhu , Nirmal Ramaswamy
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/788 ; H01L29/78 ; H01L29/792
Abstract:
Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described.
Public/Granted literature
- US20110248334A1 MULTI-LEVEL CHARGE STORAGE TRANSISTORS AND ASSOCIATED METHODS Public/Granted day:2011-10-13
Information query
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