A demodulation circuit including: a first error calculation section configured to calculate a first error in accordance with a blind method; a second error calculation section configured to calculate a second error in accordance with a DD method; an update section configured to update filter coefficients for first and second filters based on the first or second error, the first filter filtering an input signal to generate a first signal, the second filter filtering a signal representing a hard decision value for a post-equalization signal to generate a second signal; a control section configured to, in the case where the update section is updating the filter coefficients based on the second error, controlling the filter coefficients to be updated based on the first error, when the degree of the second error has exceeded a first threshold; and a generation section configured to generate the post-equalization signal based on the first and second signals.