Invention Grant
- Patent Title: Low offset input circuit and transmission system with the input circuit
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Application No.: US12453980Application Date: 2009-05-28
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Publication No.: US08358708B2Publication Date: 2013-01-22
- Inventor: Takashi Takemoto , Hiroki Yamashita , Masayoshi Yagyu
- Applicant: Takashi Takemoto , Hiroki Yamashita , Masayoshi Yagyu
- Applicant Address: JP Tokyo
- Assignee: Hitachi, Ltd.
- Current Assignee: Hitachi, Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Stites & Harbison, PLLC
- Agent Juan Carlos A. Marquez, Esq.
- Priority: JP2008-142491 20080530
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
A low offset input circuit and a signal transmission system which can accommodate a high-speed interface and achieve reduction of an offset voltage are provided. An offset voltage compensating circuit block 103 having an input circuit block 108 including an input circuit 104 and an adder-subtractor circuit block 105, switches 108, 109, a detecting circuit block 106, and an adjusting and holding circuit block 107 is provided. To compensate for an offset voltage of the input circuit block 102, an offset voltage of the input circuit block 102 is detected at the detecting circuit block 106 by turning on the switches 108, 109, and the detected offset voltage is held in the adjusting and holding circuit block 107, and negative feedback of the held offset voltage to the adder-subtractor circuit block 105 is performed. Thereby, signals Vop, Von having compensated offset voltages are outputted from the input circuit block 102.
Public/Granted literature
- US20090304092A1 Low offset input circuit and transmission system with the input circuit Public/Granted day:2009-12-10
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