Invention Grant
US08359490B2 Memory controller, system including the controller, and memory delay amount control method
失效
存储器控制器，包括控制器的系统和存储器延迟量控制方法
- Patent Title: Memory controller, system including the controller, and memory delay amount control method
- Patent Title (中): 存储器控制器，包括控制器的系统和存储器延迟量控制方法
-
Application No.: US13462689Application Date: 2012-05-02
-
Publication No.: US08359490B2Publication Date: 2013-01-22
- Inventor: Hideo Mochizuki , Kazuaki Masuda
- Applicant: Hideo Mochizuki , Kazuaki Masuda
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-133698 20080521
- Main IPC: G06F1/12
- IPC: G06F1/12
Abstract:
A memory controller coupled to a DRAM includes a delay control section including a delay holding section, and coupled to the DRAM to output a delay set value to the DRAM and a delay adjustment section coupled to the DRAM to receive data from the DRAM, and to arrange a delay amount of the received data based on the delay set value. The delay set value is stored in both the delay holding section of the memory controller and the DRAM.
Public/Granted literature
- US20120218844A1 MEMORY CONTROLLER, SYSTEM INCLUDING THE CONTROLLER, AND MEMORY DELAY AMOUNT CONTROL METHOD Public/Granted day:2012-08-30
Information query
