In one embodiment, a method of manufacturing a semiconductor device includes using a processor to generate a first three dimensional (3-D) resist profile for a first process condition using an layout mask of a target structure. The method further includes using a processor to generate a second 3-D resist profile for a second process condition using the layout mask. The first process condition includes a plurality of process variables, and the second process condition includes different values of the plurality of process variables than the first process condition. The method includes generating a 3-D process variable (PV) band profile by combining the first 3-D resist profile with the second 3-D resist profile and displaying a 3-D image of the 3-D PV band profile on a display.